Techo Rama

Toshiba Corp. has proudly announced the development of a new 3D memory cell array structure that augments cell density and data capacity with a trifling increase in the chip die size. The new structure has been created by using through-silicon vias and features pillars of stacked memory elements that go vertically through multi-stacked layers of electrode material and make use of communal peripheral circuits. While the current memory stacking technologies merely stack two-dimensional memory array on top of another and the same process is repeated again and again, the new structure doesn’t add to the increase in chip area since peripheral circuits are shared by several silicon pillars. The process of doing this involves driving a through-hole down through a stacked substrate, filling the holes with pillars of silicon, and when the gate electrode cover the silicon pillar at even gaps, a pre-shaped nitride film work as NAND cell. It has a SONOS structure – silicon-oxide-nitride-oxide- silicon Toshiba has plans to work more on this technology to make this stand equivalent to the existing structures in terms of security and reliability. Via: Pennnet