Techo Rama

Fujitsu Limited and Fujitsu Laboratories Ltd. have developed a platform technology for 45 nanometer (45nm) generation LSI logic chips that combines technologies for low power consumption and high performance interconnect. The new platform reduces the leakage current, when current is wasted in wait states to one-fifth that of previous levels and reduces interconnect induced lag time by approximately 14%. The new 45nm generation platform technologies will enable Fujitsu to offer LSI logic chips, which has higher speed, smaller size and lower power consumption to its customers. There are two problems in order to improve previous LSIs. Firstly to reduce the gate length of each transistor to make the spaces between interconnects. Second, minimize the time lag from interconnects between millions of transistors within the LSI chip for higher speed. Researchers from Fujitsu are using nano-clustering silica (NCS) with 2.25 dielectric constant, which is claimed to be the lowest of any insulating film. The lower interconnect region is suitable for the smallest interconnect spaces. NCS is an insulating material pocked with miniscule holes and enables a low dielectric value as well as high mechanical strength simultaneously. NCS is used in between different layers instead of an individual layer to further reduce interconnect capacitance. Image Credit: Designfor21st Via: Tech On