First ARM v5 instruction set architecture compliant processor, FA626TE is now available from Faraday Technology Corp. The processor has a 32bit RISC excellent computing and power-efficient capabilities for applications like infotainment systems, portable navigation devices, IP-STBs, industrial PCs, high-speed network and storage SoCs.
FA626TE processor is the first hard core, which reaches the worst clock speed of 533MHz and it is available in UMC 0.13um process. The FA626TE processor with eight pipeline stages has following features:
1) The processor has separate instruction/data caches and scratchpads
2) A buffer writer
3) A memory management unit
4) JTAG ICE interface
The CPU of the FA626TE uses four AHB or AXI interfaces, which is configured with 32/64bit widths to communicate with external memory and devices. The device has fully synthesizable core and the single-phase clock based architecture especially designed to integrate the SoC for designers. The company is expecting that the next version of 90nm UMC running on 667MHz and 800MHz in worst case would be available by the end of this year.
According to Thomas Hsieh, associate VP of central R&D at Faraday, the company is using data path optimization, process tuning, specific library and bin sorting to improve core clock speed. Thus, the company can implement the ultrahigh-performance FA626TE processor which enables the 800MHz speed in 90nm process.
Mage Credit: US design
Via: Tech On
